Memory is utilized in modern computing architectures for storing data. One type of memory is Dynamic Random Access Memory (DRAM). DRAM may provide advantages of structural simplicity, low cost and high speed in comparison to alternative types of memory.
DRAM may utilize memory cells which have one capacitor in combination with one transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. An example 1T-1C memory cell 1000 is shown in FIG. 1, with the transistor labeled T and the capacitor labeled C. The capacitor has one node coupled with a source/drain region of the transistor, and has another node coupled with a common plate, CP. The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤CP≤VCC). In some applications, the common plate is at a voltage of about one-half VCC (i.e., about VCC/2). The transistor has a gate coupled to a wordline WL (i.e., access line), and has a source/drain region coupled to a bitline BL (i.e., digit line or sense line). In operation, an electrical field generated by voltage along the wordline may gatedly couple the bitline to the capacitor during read/write operations.
Another prior art memory cell configuration utilizes two capacitors in combination with two transistors. Such configuration may be referred to as a 2T-2C memory cell. A 2T-2C memory cell 1010 is schematically illustrated in FIG. 2. The two transistors of the memory cell are labeled T1 and T2, and may be referred to as first and second transistors, respectively. The two capacitors are labeled C1 and C2, and may be referred to as first and second capacitors, respectively.
A source/drain region of the first transistor T1 connects with a node of the first capacitor C1, and the other source/drain region of the first transistor T1 connects with a first comparative bitline BL-T. A gate of the first transistor T1 connects with a wordline WL. A source/drain region of the second transistor T2 connects with a node of the second capacitor C2, and the other source/drain region of the second transistor T2 connects with a second comparative bitline BL-C. A gate of the second transistor T2 connects with the wordline WL. Each of the first and second capacitors C1 and C2 has a node electrically coupled with a common plate CP.
The comparative bitlines BL-T and BL-C extend to a sense amplifier SA which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell 1010. The bitline BL-T may be referred to as a true bitline, and the bitline BL-C may be referred to as a complementary bitline. The terms “true” and “complementary” are arbitrary, and merely indicate that the bitline values of BL-T and BL-C are to be compared to one another.
It would be desirable to develop architectures which incorporate memory into highly-integrated arrangements in order to conserve valuable real estate of a semiconductor chip.